(1) Field of the Invention
The present invention relates to the fabrication of dynamic random access memory (DRAM) devices, and more particularly to a method for fabricating cylindrical stacked capacitors with node contacts for DRAM cells using a single photoresist masking step.
(2) Description of the Prior Art
These DRAM circuits are used extensively in the electronics industry, and particularly in the computer industry for electrical data storage. The DRAM circuits consist of an array of individual memory cells, each cell consisting of an access transistor, usually a field effect transistor (FET), and a single storage capacitor. Information is stored on the cell as charge on the capacitor, which represents a unit of data (bit), and is accessed by read/write circuits on the periphery of the chip.
One conventional method to achieve a high density of memory cells on a DRAM chip is to form a capacitor node contact to one of the source/drain areas of the FET in each of the memory cells, and then to form a bottom electrode aligned over the node contact. In the next generation of semiconductor technology, the minimum feature sizes will be 0.25 micrometers or less. At these feature sizes, misalignment of the bottom electrode to the node contact can result in processing and reliability problems. Therefore it is desirable to make a DRAM device having the capacitor bottom electrode self-aligned to the node contact. In recent years the cost of DRAM devices has dramatically decreased, and therefore there is a strong need to also provide a more cost-effective manufacturing process in which the number of processing steps is minimized.
Numerous methods of making DRAM circuits with stacked capacitors are reported in the literature. Several methods for making DRAM capacitors are cited below. However, the methods require aligning the bottom electrode to the node contact and/or require additional masking steps. Alternatively, other methods form the capacitor adjacent to the bit line and therefore require additional area for memory cells. For example, in U.S. Pat. No. 5,677,223 and U.S. Pat. No. 5,728,618 to Tseng, the capacitor is not self-aligned to the node contact, in U.S. Pat. No. 5,712,202 to Liaw the bottom electrode is not self-aligned to the node contact. In U.S. Pat. No. 5,733,808 to Tseng, additional masking steps are required for making the node contact and the bottom electrode. U.S. Pat. No. 5,604,146 to Tseng, the capacitor bottom electrode is not self-aligned to the node contact. Kin in U.S. Pat. No. 5,580,811 forms the capacitor adjacent to the bit line and therefore requires additional cell area on the chip. Tseng in U.S. Pat. No. 5,705,438 forms the bit line adjacent to and in the same plane as the capacitor, and therefore requires additional cell area on the chip. In U.S. Pat. No. 5,453,633 to Yun, the bottom electrode is not self-aligned to the node contact and additional masking steps are required.
Therefore, there is still a need to form stacked capacitors in which the capacitor bottom electrode is self-aligned to the capacitor node contact using a single photoresist mask.